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40MSPS 16-bit CCD Digitiser
DESCRIPTION
The WM8214 is a 16-bit analogue front end/digitiser IC which processes and digitises the analogue output signals from CCD sensors or Contact Image Sensors (CIS) at pixel sample rates of up to 40MSPS. The device includes three analogue signal processing channels each of which contains Reset Level Clamping, Correlated Double Sampling and Programmable Gain and Offset adjust functions. Three multiplexers allow single channel processing. The output from each of these channels is time multiplexed into a single high-speed 16-bit Analogue to Digital Converter. The digital output data is available in 8-bit wide multiplexed format and there is also an optional single byte output mode, or 4-bit multiplexed LEGACY mode. An internal 4-bit DAC is supplied for internal reference level generation. This may be used during CDS to reference CIS signals or during Reset Level Clamping to clamp CCD signals. An external reference level may also be supplied. ADC references are generated internally, ensuring optimum performance from the device. Using an analogue supply voltage of 3.3V and a digital interface supply of 3.3V, the WM8214 typically only consumes 390mW.
WM8214
FEATURES
* * * * * * * * * * * * * * * * 16-bit ADC 40MSPS conversion rate Low power - 390mW typical 3.3V single supply operation Single, 2 or 3 channel operation Correlated double sampling Programmable gain (9-bit resolution) Programmable offset adjust (8-bit resolution) Flexible clamp control with programmable clamp voltage Flexible timing, can be made compatible with WM819X and WM815X parts. 8-bit wide multiplexed data output format 8-bit only output mode 4-bit LEGACY multiplexed nibble mode Internally generated voltage references 28-lead SSOP package, pin compatible with WM8199 Serial control interface
APPLICATIONS
* * * * High speed USB2.0 compatible scanners Multi-function peripherals High-performance CCD sensor interface Digital Copiers
BLOCK DIAGRAM
VRLC/VBIAS RSMP VSMP MCLK AVDD DVDD1 DVDD2 VRT VRX VRB
CLMP
RS V S
TIMING CONTROL
R G B M U X 8
WM8214
VREF/BIAS OFFSET DAC + PGA
9
OEB + I/P SIGNAL POLARITY ADJUST M U X 16BIT ADC DATA O/P PORT OP[0] OP[1] OP[2] OP[3] OP[4] OP[5] OP[6] OP[7]/SDO
RINP
RLC
CDS
R G B M U X
GINP
RLC
CDS
8
+ OFFSET DAC
PGA
9
+ I/P SIGNAL POLARITY ADJUST
BINP
RLC
CDS
8
+ OFFSET DAC
PGA
9
+ I/P SIGNAL POLARITY ADJUST
RLC DAC
4
CONFIGURABLE SERIAL CONTROL INTERFACE
SEN SCK SDI
AGND1
AGND2
DGND
WOLFSON MICROELECTRONICS plc
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Production Data, August 2008, Rev 4.4 Copyright (c)2008 Wolfson Microelectronics plc.
WM8214 TABLE OF CONTENTS
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DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................5 THERMAL PERFORMANCE .................................................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6
INPUT VIDEO SAMPLING ............................................................................................ 8 SERIAL INTERFACE................................................................................................... 10
INTERNAL POWER ON RESET CIRCUIT ..........................................................11 DEVICE DESCRIPTION.......................................................................................13
INTRODUCTION ......................................................................................................... 13 INPUT SAMPLING ...................................................................................................... 13 RESET LEVEL CLAMPING (RLC)............................................................................... 14 CDS/NON-CDS PROCESSING................................................................................... 16 OFFSET ADJUST AND PROGRAMMABLE GAIN ...................................................... 17 ADC INPUT BLACK LEVEL ADJUST.......................................................................... 18 OVERALL SIGNAL FLOW SUMMARY........................................................................ 19 CALCULATING THE OUTPUT CODE FOR A GIVEN INPUT ..................................... 20 OUTPUT FORMATS ................................................................................................... 21 REFERENCES ............................................................................................................ 21 POWER MANAGEMENT ............................................................................................ 21 LINE-BY-LINE OPERATION ....................................................................................... 22 CONTROL INTERFACE.............................................................................................. 22 NORMAL OPERATING MODES ................................................................................. 24 LEGACY MODE INFORMATION................................................................................. 25 LEGACY OPERATING MODES .................................................................................. 26 LEGACY MODE TIMING DIAGRAMS ......................................................................... 27
DEVICE CONFIGURATION .................................................................................29
REGISTER MAP ......................................................................................................... 29 REGISTER MAP DESCRIPTION ................................................................................ 30
APPLICATIONS INFORMATION .........................................................................34
RECOMMENDED EXTERNAL COMPONENTS .......................................................... 34 RECOMMENDED EXTERNAL COMPONENT VALUES ............................................. 34
PACKAGE DIMENSIONS ....................................................................................35 IMPORTANT NOTICE ..........................................................................................36
ADDRESS: .................................................................................................................. 36
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WM8214
PIN CONFIGURATION
RINP AGND2 DVDD1 OEB VSMP RSMP MCLK DGND SEN DVDD2 SDI SCK OP[0] OP[1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GINP BINP VRLC/VBIAS VRX VRT VRB AGND1 AVDD OP[7]/SDO OP[6] OP[5] OP[4] OP[3] OP[2]
ORDERING INFORMATION
DEVICE WM8214SCDS/V WM8214SCDS/RV Note: Reel quantity = 2,000 TEMP. RANGE 0 to 70oC 0 to 70oC PACKAGE 28-lead SSOP (Pb-free) 28-lead SSOP (Pb-free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL2 MSL2 PEAK SOLDERING TEMPERATURE 260oC 260oC
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WM8214 PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 NAME RINP AGND2 DVDD1 OEB VSMP RSMP MCLK DGND SEN DVDD2 SDI SCK TYPE Analogue input Supply Supply Digital input Digital input Digital input Digital input Supply Digital input Supply Digital input Digital input DESCRIPTION Red channel input video. Analogue ground reference.
Production Data
Digital supply for logic and clock generator. This must be operated at the same potential as AVDD. Output Hi-Z control, all digital outputs disabled when register bit OEB = 1 or register bit OPD = 1. Video sample timing pulse. Reset sample timing pulse (also used for RLC control). Master (ADC) clock. This determines the ADC conversion rate. Digital ground reference. Enables the serial interface when high. Digital supply, all digital I/O pins. Serial data input. Serial clock. Digital multiplexed output data bus. ADC output data (d15:d0) is available in multiplexed format as shown. See `Output Formats' description in Device Description section for details of other output modes. A B d0 d1 d2 d3 d4 d5 d6 d7
13 14 15 16 17 18 19 20
OP[0] OP[1] OP[2] OP[3] OP[4] OP[5] OP[6] OP[7]/SDO
Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output
d8 d9 d10 d11 d12 d13 d14 d15
Alternatively, pin OP[7]/SDO may be used to output register read-back data when register bit OEB = 0, OPD = 0 and SEN has been pulsed high. See Serial Interface description in Device Description section for further details. 21 22 23 24 25 26 AVDD AGND1 VRB VRT VRX VRLC/VBIAS Supply Supply Analogue output Analogue output Analogue output Analogue I/O Analogue supply. This must be operated at the same potential as DVDD1. Analogue ground reference. Lower reference voltage. This pin must be connected to AGND via a decoupling capacitor. Upper reference voltage. This pin must be connected to AGND via a decoupling capacitor. Input return bias voltage. This pin must be connected to AGND via a decoupling capacitor. Selectable analogue output voltage for RLC or single-ended bias reference. This pin would typically be connected to AGND via a decoupling capacitor. VRLC can be externally driven if programmed Hi-Z. Blue channel input video. Green channel input video.
27 28
BINP GINP
Analogue input Analogue input
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WM8214
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION Analogue supply voltage: AVDD Digital supply voltages: DVDD1 - 2 Digital ground: DGND Analogue grounds: AGND1 - 2 Digital inputs, digital outputs and digital I/O pins Analogue inputs (RINP, GINP, BINP) Other pins Operating temperature range: TA Storage temperature after soldering Notes: 1. 2. GND denotes the voltage of any ground pin. AGND1, AGND2 and DGND pins are intended to be operated at the same potential. Differential voltages between these pins will degrade performance. MIN GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V 0C -65C MAX GND + 5V GND + 5V GND + 0.3V GND + 0.3V DVDD2 + 0.3V AVDD + 0.3V AVDD + 0.3V +70C +150C
RECOMMENDED OPERATING CONDITIONS
CONDITION Operating temperature range Analogue supply voltage Digital core supply voltage Digital I/O supply voltage Notes: 1. DVDD2 should be operated at the same potential as DVDD1 0.3V. SYMBOL TA AVDD DVDD1 DVDD2 MIN 0 2.97 2.97 2.97 3.3 3.3 3.3 TYP MAX 70 3.63 3.63 3.63 UNITS C V V V
THERMAL PERFORMANCE
PARAMETER Performance Thermal resistance - junction to case Thermal resistance - junction to ambient Notes: 1. Figures given are for package mounted on 4-layer FR4 according to JESD51-5 and JESD51-7. RJC RJA Tambient = 25C 23.9 67.1 C/W C/W SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
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WM8214 ELECTRICAL CHARACTERISTICS
Test Conditions AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25C, MCLK = 40MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP
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MAX
UNIT
Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions) Conversion rate Full-scale input voltage range (see Note 1) LOWREFS=0, Max Gain LOWREFS=0, Min Gain LOWREFS=1, Max Gain LOWREFS=1, Min Gain Input signal limits (see Note 2) Input Capacitance Input Impedance Full-scale transition error Zero-scale transition error Differential non-linearity Integral non-linearity Channel to channel gain matching Total output noise References Upper reference voltage Lower reference voltage Input return bias voltage Diff. reference voltage (VRT-VRB) Output resistance VRT, VRB, VRX Reset-Level Clamp (RLC) circuit/ Reference Level DAC RLC switching impedance VRLC short-circuit current VRLC output resistance VRLC Hi-Z leakage current Reference RLCDAC resolution Reference RLCDAC step size Reference RLCDAC step size Reference RLCDAC output voltage at code 0(hex) Reference RLCDAC output voltage at code 0(hex) Reference RLCLDAC output voltage at code F(hex) Reference RLCDAC output voltage at code F(hex) RLCDAC RLCDAC VRLCSTEP VRLCSTEP VRLCBOT VRLCBOT VRLCTOP VRLCTOP DNL INL AVDD=3.3V RLCDACRNG=0 RLCDACRNG=1 AVDD=3.3V, RLCDACRNG=0 RLCDACRNG=1 AVDD=3.3V, RLCDACRNG=0 RLCDACRNG = 1 -0.5 +/-1 VRLC = 0 to AVDD 4 0.173 0.11 0.4 0.4 3.0 2.05 +0.5 50 2 2 1 mA A bits V/step V/step V V V V LSB LSB VRT VRB VRX VRTB LOWREFS=0 LOWREFS=1 0.90 LOWREFS=0 LOWREFS=1 LOWREFS=0 LOWREFS=1 1.95 0.95 2.05 1.85 1.05 1.25 1.25 1.0 0.6 1 1.10 2.25 1.25 V V V V Min Gain Max Gain DNL INL Gain = 0dB; PGA[8:0] = 18(hex) Gain = 0dB; PGA[8:0] = 18(hex) VIN AGND-0.3 10 50 20 20 1 25 1% 15 140 40 0.25 3.03 0.15 1.82 AVDD+0.3 MSPS Vp-p Vp-p Vp-p Vp-p V pF mV mV LSB LSB % LSB rms LSB rms
Notes: 1. Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC full-scale input range. 2. Input signal limits are the limits within which the full-scale input voltage signal must lie.
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WM8214
Test Conditions AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25C, MCLK = 40MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Offset DAC, Monotonicity Guaranteed Resolution Differential non-linearity Integral non-linearity Step size Output voltage Programmable Gain Amplifier Resolution Gain equation Max gain, each channel Min gain, each channel Channel Matching Analogue to Digital Converter Resolution Speed Full-scale input range (2*(VRT-VRB)) DIGITAL SPECIFICATIONS Digital Inputs High level input voltage Low level input voltage High level input current Low level input current Input capacitance Digital Outputs High level output voltage Low level output voltage High impedance output current Digital IO Pins Applied high level input voltage Applied low level input voltage High level output voltage Low level output voltage Low level input current High level input current Input capacitance High impedance output current Supply Currents Total supply current - active (Analogue and Digital) (Three channel mode) Analogue supply current -active (three channel mode) Digital supply current - active (three channel mode) Supply current - full power down mode 118 mA VIH VIL VOH VOL IIL IIH CI IOZ 5 1 IOH = 1mA IOL = 1mA DVDD2 - 0.5 0.5 1 1 0.7 DVDD2 0.2 DVDD2 V V V V A A pF A VOH VOL IOZ IOH = 1mA IOL = 1mA DVDD2 - 0.5 0.5 1 V V A VIH VIL IIH IIL CI 5 0.7 DVDD2 0.2 DVDD2 1 1 V V A A pF LOWREFS=0 LOWREFS=1 2 1.2 16 40 bits MSPS V V GMAX GMIN 9
7.34 0.66 + * PGA [ 8 : 0 ] 511
8 DNL INL Code 00(hex) Code FF(hex) 0.1 0.25 2.04 -260 +260 0.5 1
bits LSB LSB mV/step mV mV bits V/V V/V V/V 5 %
7.8 0.68 1
105 13 20
mA mA A
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WM8214
INPUT VIDEO SAMPLING
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Figure 1 Three-channel CDS Input Video Timing
Figure 2 Two-channel CDS Input Video Timing
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WM8214
Figure 3 Single-channel CDS Input Video Timing Notes: 1. The relationship between input video and sampling is controlled by VSMP and RSMP. 2. When VSMP is high the input video signal is connected to the Video sampling capacitors. 3. When RSMP is high the input video signal is connected to the Reset sampling capacitors. 4. RSMP must not go high before the first falling edge of MCLK after VSMP goes low. 5. It is required that the falling edge of VSMP should occur before the rising edge of MCLK. 6. In 1-channel CDS mode it is not possible to have a equally spaced Video and Reset sample points with a 40MHz MCLK 7. Non-CDS operation is also possible; RSMP is not required in this mode. Test Conditions AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25C, MCLK = 40MHz unless otherwise stated. PARAMETER MCLK period MCLK high period MCLK low period RSMP pulse high time VSMP pulse high time RSMP falling to VSMP rising time MCLK rising to VSMP rising time MCLK falling to VSMP falling time VSMP falling to MCLK rising time
2
SYMBOL tPER tMCLKH tMCLKL tRSD tVSD tRSFVSR tMRVSR tMFVSF tVSFMR tMF1RS tPR3 tPR2 tPR1 tPD LAT
TEST CONDITIONS
MIN 25 11.3 11.3 5 5 0 3 5 1 1 75 50 25
TYP 12.5 12.5
MAX
UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
1st MCLK falling edge after VSMP falling to RSMP rising time 3-channel mode pixel rate 2-channel mode pixel rate 1-channel mode pixel rate Output propagation delay Output latency. From 1st rising edge of MCLK after VSMP falling to data output Notes: 1. 2.
5 7
10
ns MCLK periods
Parameters are measured at 50% of the rising/falling edge. In Single-Channel mode, if the VSMP falling edge is placed more than 3ns before the rising edge of MCLK the output amplitude of the WM8214 will decrease.
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WM8214
SERIAL INTERFACE
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Figure 4 Serial Interface Timing
Test Conditions AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25C, MCLK = 40MHz unless otherwise stated. PARAMETER SCK period SCK high SCK low SDI set-up time SDI hold time SCK Rising to SEN Rising SCK Falling to SEN Falling SEN to SCK set-up time SEN pulse width SEN low to SDO = Register data SCK low to SDO = Register data SCK low to SDO = ADC data SYMBOL tSPER tSCKH tSCKL tSSU tSH tSCRSER tSCFSEF tSEC tSEW tSERD tSCRD tSCRDZ TEST CONDITIONS MIN 83.3 37.5 37.5 6 6 37.5 12 12 60 30 30 30 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns
Note: 1. Parameters are measured at 50% of the rising/falling edge
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WM8214
INTERNAL POWER ON RESET CIRCUIT
Figure 5 Internal Power On Reset Circuit Schematic The WM8214 includes an internal Power-On-Reset Circuit, as shown in Figure 5, which is used reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and monitors DVDD1. It asserts PORB low if AVDD or DVDD1 is below a minimum threshold.
Figure 6 Typical Power up Sequence where AVDD is Powered before DVDD1
Figure 6 shows a typical power-up sequence where AVDD is powered up first. When AVDD rises above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. Now AVDD is at full supply level. Next DVDD1 rises to Vpord_on and PORB is released high and all registers are in their default state and writes to the control interface may take place. On power down, where AVDD falls first, PORB is asserted low whenever AVDD drops below the minimum threshold Vpora_off.
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WM8214
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Figure 7 Typical Power up Sequence where DVDD1 is Powered before AVDD
Figure 7 shows a typical power-up sequence where DVDD1 is powered up first. It is assumed that DVDD1 is already up to specified operating voltage. When AVDD goes above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. When AVDD rises to Vpora_on, PORB is released high and all registers are in their default state and writes to the control interface may take place. On power down, where DVDD1 falls first, PORB is asserted low whenever DVDD1 drops below the minimum threshold Vpord_off.
SYMBOL Vpora Vpora_on Vpora_off Vpord_on Vpord_off
TYP 0.6 1.2 0.6 0.7 0.6
UNIT V V V V V
Table 1 Typical POR Operation (typical values, not tested)
Note: It is recommended that every time power is cycled to the WM8214 a software reset is written to the software register to ensure that the contents of the control registers are at their default values before carrying out any other register writes.
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WM8214
DEVICE DESCRIPTION
INTRODUCTION
A block diagram of the device showing the signal path is presented on the front page of this datasheet. The WM8214 samples up to three inputs (RINP, GINP and BINP) simultaneously. The device then processes the sampled video signal with respect to the video reset level or an internally/externally generated reference level using between one and three processing channels. Each processing channel consists of an Input Sampling block with optional Reset Level Clamping (RLC) and Correlated Double Sampling (CDS), an 8-bit programmable offset DAC and a 9-bit Programmable Gain Amplifier (PGA). The ADC then converts each resulting analogue signal to a 16-bit digital word. The digital output from the ADC is presented on an 8-bit wide bus. On-chip control registers determine the configuration of the device, including the offsets and gains applied to each channel. These registers are programmable via a serial interface. The WM8214 has been designed to have a high degree of compatibility with previous generations of Wolfson AFEs. By setting the LEGACY register bit the device adopts the same timing as the WM819x and WM815x families of AFEs. The control interface is also compatible.
INPUT SAMPLING
The WM8214 can sample and process one to three inputs through one to three processing channels as follows: Colour Pixel-by-Pixel: The three inputs (RINP, GINP and BINP) are simultaneously sampled for each pixel and a separate channel processes each input. The signals are then multiplexed into the ADC, which converts all three inputs within the pixel period. Two Channel Pixel-by-pixel: Two input channels (RINP and GINP) are simultaneously sampled for each pixel and a separate channel processes each input. The signals are then multiplexed into the ADC, which converts both inputs within the pixel period. The unused Blue channel is powered down when this mode is selected. Monochrome: A single chosen input (RINP, GINP, or BINP) is sampled, processed by the corresponding channel, and converted by the ADC. The choice of input and channel can be changed via the control interface, e.g. on a line-by-line basis if required. The unused channels are powered down when this mode is selected. Colour Line-by-Line: A single input (RINP) is sampled and multiplexed into the red channel for processing before being converted by the ADC. The registers which are applied to the PGA and Offset DAC can be switched in turn (RINP GINP BINP RINP...) by applying pulses to the RSMP pin. This is known as auto-cycling. Alternatively, other sequences can be generated via the control registers. This mode causes the unused blue and green channels to be powered down. Refer to the Line-by-Line Operation section for more details.
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RESET LEVEL CLAMPING (RLC)
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To ensure that the signal applied to the WM8214 lies within the supply voltage range (0V to AVDD) the output signal from a CCD is usually level shifted by coupling through a capacitor, CIN. The RLC circuit clamps the WM8214 side of this capacitor to a suitable voltage through a CMOS switch during the CCD reset period. In order for clamping to produce sensible results the input voltage during the clamping must be a consistent value. The WM8214 allows the user to control the RLC switch in a variety of ways as illustrated in Figure 8. This figure shows a single channel, however all 3 channels are identical, each with its own clamp switch controlled by the common CLMP signal. The method of control chosen depends upon the characteristics of the input video. The RLCEN register bit must be set to 1 to enable clamping, otherwise the RLC switch cannot be closed (by default RLCEN=1).
Figure 8 RLC Clamp Control Options When an input waveform has a stable reference level on every pixel it may be desirable to clamp every pixel during this period. Setting CLAMPCTRL=0 means that the RLC switch is closed whenever the RSMP input pin is high, as shown in Figure 9.
INPUT VIDEO SIGNAL MCLK VSMP RSMP RLC switch control "CLMP" (RLCEN=1,CLMPCTRL=0)
reference ("black") level video level
Video sample taken on fallling edge of VSMP Reset/reference sample taken on fallling edge of RSMP RLC switch closed when RSMP=1
Figure 9 Reset Level Clamp Operation (CLAMPCTRL=0), CDS operation shown, non-CDS also possible
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WM8214
In situations where the input video signal does not have a stable reference level it may be necessary to clamp only during those pixels which have a known state (e.g. the dummy, or "black" pixels at the start or end of a line of most image sensors). This is known as line-clamping and relies on the input capacitor to hold the DC level between clamp intervals. In non-CDS mode (CDS=0) this can be done directly by controlling the RSMP input pin to go high during the black pixels only. Alternatively it is possible to use RSMP to identify the black pixels and enable the clamp at the same time as the input is being sampled (i.e. when VSMP is high and RSMP is high). This mode is enabled by setting CLAMPCTRL=1 and the operation is shown in Figure 10.
unstable reference level
INPUT VIDEO SIGNAL MCLK VSMP RSMP RLC switch control, "CLMP" (RLCEN=1,CLMPCTRL=1)
dummy or "black" pixel video level
Video and reference sample taken on fallling edge of VSMP
RLC switch closed when RSMP=1 && VSMP=1 (during "black" pixels)
Figure 10 Reset Level Clamp Operation (CLAMPCTRL=1), non-CDS mode only When in LEGACY mode all timing, including the RLC switch timing, is derived from MCLK and VSMP. MCLK operates at double the ADC conversion rate and VSMP determines the sample rate of the device. Reset Level Clamping in LEGACY mode is only possible in CDS mode and the time at which the clamp switch is closed is concurrent with the reset sample period, RS, as shown in Figure 11. RLC can be enabled on a pixel by pixel basis under control of the RSMP input pin. If RSMP is high when VSMP is high and is sampled by MCLK then clamping will be enabled for that input sample at the time determined by CDSREF[1:0]. If RSMP is low at this point then the RLC switch will not be closed for that input sample. If RLC is required on every pixel then the RSMP pin can be constantly held high in LEGACY mode.
Figure 11 LEGACY Mode RLC and Sampling (LEGACY=1)
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Table 2 summarises the various options for control of the Reset Level Clamp switch.
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RLCEN LEGACY CLAMPCTRL
LINEBYLINE &&ACYC
OUTCOME
USE
0 1
X 0
X 0
X X
RLC is not enabled. RLC switch is always open. RLC switch is controlled directly from RSMP input pin: RSMP=0: switch is open RMSP=1: switch is closed VSMP applied as normal, RSMP is used to indicate the location of black pixels RLC switch is controlled by logical combination of RSMP and VSMP: RSMP && VSMP = 0: switch is open RSMP && VSMP = 1: switch is closed LEGACY mode RLC works in the same fashion as the WM819x series, where the RSMP pin is equivalent to the RLC/ACYC pin on those devices. The reset sample clock which is generated by the LEGACY internal timing generator is gated with the RSMP pin to produce the RLC control signal CL (see Figure 11) : CL=0: clamp switch open CL=1: clamp switch closed In this mode the RSMP pin is used to control autocycling so can't be used for clamp control. Register bit CLAMPCTRL controls whether RLC is enabled or not. CLAMPCTRL=0, RLC is disabled CLAMPCTRL=1, RLC is enabled and every pixel will be clamped during the control signal CL (see Figure 11).
When input is DC coupled and within supply rails. When user explicitly provides a reset sample signal and the input video waveform has a suitable reset level. When you wish to clamp during the video period of black pixels or there is no stable per-pixel reference level.
1
0
1
X
1
1
X
X
When using the LEGACY timing mode.
X
1
0 1
1
When auto-cycling in LEGACY mode.
Table 2 Reset Level Clamp Control Summary
CDS/NON-CDS PROCESSING
For CCD type input signals, containing a fixed reference/reset level, the signal may be processed using Correlated Double Sampling (CDS), which will remove pixel-by-pixel common mode noise. With CDS processing the input waveform is sampled at two different points in time for each pixel, once during the reference/reset level and once during the video level. To sample using CDS, register bit CDS must be set to 1 (default). This causes the signal reference to come from the video reference level as shown in Figure 12. The video sample is always taken on the falling edge of the input VSMP signal (VS). In CDS-mode the reset level is sampled on the falling edge of the RSMP input signal (RS). For input signals that do not contain a reference/reset level (e.g. CIS sensor signals), non-CDS processing is used (CDS=0). In this case, the video level is processed with respect to the voltage on pin VRLC/VBIAS. The VRLC/VBIAS voltage is sampled at the same time as VSMP samples the video level in this mode. In LEGACY mode the input video signal is always sampled on the 1st rising edge of MCLK after VSMP has gone low (VS) regardless of the operating mode. If in non-CDS mode (CDS=0) the voltage on the VRLC/VBIAS pin is also sampled at this point. In CDS-mode (CDS=1) the position of the reset sample (RS) can be varied, under control of the CDSREF[1:0] register bits, as shown in Figure 11.
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WM8214
CIN
RINP or GINP or BINP
VS
'Video' sample capacitor
RLC switch closed= 50 Ohm
CLMP
RS (if CDS=1) or VS (if CDS=0)
CDS=1 CDS=0
'Reference' sample capacitor
CONTROL INTERFACE
CDS
VRLC/ VBIAS
4-BIT RLCDAC
RLCDAC[3:0]
VRLCDACEN
Figure 12 CDS/non-CDS Input Configuration
OFFSET ADJUST AND PROGRAMMABLE GAIN
The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset DAC to compensate for offsets and then amplified by a 9-bit PGA. The gain and offset for each channel are independently programmable by writing to control bits DAC[7:0] and PGA[7:0]. The gain characteristic of the WM8214 PGA is shown in Figure 13. Figure 14 shows the maximum device input voltage that can be gained up to match the ADC full-scale input range (default=2V). In colour line-by-line mode the gain and offset coefficients for each colour can be multiplexed in order (Red Green Blue Red...) by pulsing the RSMP pin, or controlled via the ACYC and INTM[1:0] bits. Refer to the Line-by-Line Operation section for more details.
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3.5 Max i/p V oltage LOWREFS=0 Max i/p V oltage LOWREFS=1 2.5
7
3
6
5 PGA Gain (V/V)
Input Voltage Range (V)
0 128 256 Gain Code (PGA[8:0]) 384 512
2
4
1.5
3
2
1
1
0.5
0
0 0 128 256 Gain Code (PGA[8:0]) 384 512
Figure 13 PGA Gain Characteristic
Figure 14 Peak Input Voltage to Match ADC Full-scale Range
ADC INPUT BLACK LEVEL ADJUST
The output from the PGA can be offset to match the full-scale range of the differential ADC (2*[VRTVRB]). For negative-going input video signals, a black level (zero differential) output from the PGA should be offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. This will give an output code of FFFF (hex) from the WM8214 for zero input. If code zero is required for zero differential input then the INVOP bit should be set. For positive going input signals the black level should be offset to the bottom of the ADC range by setting PGAFS[1:0]=11. This will give an output code of 0000 (hex) from the WM8214 for zero input. Bipolar input video is accommodated by setting PGAFS[1:0]=00 or PGAFS[1:0]=01. Zero differential input voltage gives mid-range ADC output, 7FFF (hex).
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WM8214
Figure 15 ADC Input Black Level Adjust Settings
OVERALL SIGNAL FLOW SUMMARY
Figure 16 represents the processing of the video signal through the WM8214.
OUTPUT INVERT BLOCK
INPUT SAMPLING OFFSET DAC PGA BLOCK BLOCK BLOCK
ADC BLOCK
V1
V2
VIN CDS = 1 VRESET CDS = 0 VVRLC CDACPD=1
+
-
+
+
X
V3
analog
x (65535/VFS) D +0 if PGAFS[1:0]=11 1 +65535 if PGAFS[1:0]=10 +32768 if PGAFS[1:0]=0x digital
D2
OP[7:0]
PGA gain A= 0.66+PGA[8:0]x7.34/511
D2 = D1 if INVOP = 0 D2 = 65535-D1 if INVOP = 1
Offset DAC
260mV*(DAC[7:0]-127.5)/127.5
CDACPD=0
VIN is RINP or GINP or BINP VRESET is VIN sampled during reset clamp VRLC is voltage applied to VRLC/VBIAS pin CDS, CDACPD,CDAC[3:0], DAC[7:0], PGA[8:0], PGAFS[1:0] and INVOP are set by programming internal control registers. CDS=1 for CDS, 0 for non-CDS
RLC DAC
See parametrics for DAC voltages.
Figure 16 Overall Signal Flow The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the difference between the input video level VIN and the voltage on the VRLC/VBIAS pin, VVRLC, optionally set via the RLC DAC. The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the black level of the input signal towards 0V, producing V2. The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range, outputting voltage V3. The ADC BLOCK then converts the analogue signal, V3, to a 16-bit unsigned digital output, D1. The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D2.
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CALCULATING THE OUTPUT CODE FOR A GIVEN INPUT
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The following equations describe the processing of the video and reset level signals through the WM8214. The values of V1, V2 and V3 are often calculated in reverse order during device setup. The PGA value is written first to set the input Voltage range, the Offset DAC is then adjusted to compensate for any Black/Reset level offsets and finally the RLC DAC value is set to position the reset level correctly during operation. Note: Refer to Applications Note WAN0123 for detailed information on device calibration procedures.
INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING
If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the input video. V1 = VIN - VRESET Eqn. 1
If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted instead. V1 = VIN - VVRLC Eqn. 2
If VRLCDACPD = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS. If VRLCDACPD = 0, VVRLC is the output from the internal RLC DAC. VVRLC = (VRLCSTEP RLC DAC[3:0]) + VRLCBOT Eqn. 3
VRLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC.
OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST
The resultant signal V1 is added to the Offset DAC output. V2 = V1 + {260mV (DAC[7:0]-127.5) } / 127.5 Eqn. 4
PGA NODE: GAIN ADJUST
The signal is then multiplied by the PGA gain. V3 = V2 (0.66 + PGA[8:0]x7.34/511) Eqn. 5
ADC BLOCK: ANALOGUE-DIGITAL CONVERSION
The analogue signal is then converted to a 16-bit unsigned number, with input range configured by PGAFS[1:0]. D1[15:0] = INT{ (V3 /VFS) 65535} + 32767 D1[15:0] = INT{ (V3 /VFS) 65535} D1[15:0] = INT{ (V3 /VFS) 65535} + 65535 PGAFS[1:0] = 00 or 01 PGAFS[1:0] = 11 PGAFS[1:0] = 10 Eqn. 6 Eqn. 7 Eqn. 8
where the ADC full-scale range, VFS = 2V when LOWREFS=0 and VFS = 1.2V when LOWREFS=1.
OUTPUT INVERT BLOCK: POLARITY ADJUST
The polarity of the digital output may be inverted by control bit INVOP. D2[15:0] = D1[15:0] (INVOP = 0) D2[15:0] = 65535 - D1[15:0] (INVOP = 1) Eqn. 9 Eqn. 10
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WM8214
The output from the WM8214 can be presented in several different formats under control of the OPFORM[1:0] register bits as shown in Figure 17.
OUTPUT FORMATS
MCLK tPD 8-bit multiplexed OP[7:0]
A B A B A B A B
tPD
8-bit parallel OP[7:0]
A A A A
8-bit multiplexed (LEGACY=1) OP[7:0] 8-bit parallel (LEGACY=1) OP[7:0]
A A A B A B
4-bit multiplexed (LEGACY=1) OP[7:4]
A B C D A B C D
Figure 17 Output Data Formats
OUTPUT FORMAT 8+8-bit multiplexed 8-bit parallel 4+4+4+4-bit (nibble)
OPFORM[1:0] LEGACY 00, 10 01 11 X X 1
OUTPUT PINS OP[7:0] OP[7:0] OP[7:4]
OUTPUT A = d15, d14, d13, d12, d11, d10, d9, d8 B = d7, d6, d5, d4, d3, d2, d1,d0 A = d15, d14, d13, d12, d11, d10, d9, d8 A = d15, d14, d13, d12 B = d11, d10, d9, d8 C = d7, d6, d5, d4 D = d3, d2, d1, d0
Table 3 Details of Output Data Formats (as shown in Figure 17).
REFERENCES
The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins VRT and VRB, where they must be decoupled to ground. Pin VRX is driven by a similar buffer, and also requires decoupling. The output buffer from the RLCDAC also requires decoupling at pin VRLC/VBIAS.
POWER MANAGEMENT
Power management for the device is performed via the Control Interface. By default the device is fully enabled. The EN bit allows the device to be fully powered down when set low. Individual blocks can be powered down using the bits in Setup Register 5. When in MONO or TWOCHAN mode the unused input channels are automatically disabled to reduce power consumption.
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LINE-BY-LINE OPERATION
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Certain linear sensors give colour output on a line-by-line basis. i.e. a full line of red pixels followed by a line of green pixels followed by a line of blue pixels. Often the sensor will have only a single output onto which these outputs are time multiplexed. The WM8214 can accommodate this type of input by setting the LINEBYLINE register bit high. When in this mode the green and blue input PGAs are disabled to save power. The analogue input signal should be connected to the RINP pin. The offset and gain values that are applied to the Red input channel can be selected, by internal multiplexers, to come from the Red, Green or Blue offset and gain registers. This allows the gain and offset values for each of the input colours to be setup individually at the start of a scan. When register bit ACYC=0 the gain and offset multiplexers are controlled via the INTM[1:0] register bits. When INTM=00 the red offset and gain control registers are used to control the Red input channel, INTM=01 selects the green offset and gain registers and INTM=10 selects the blue offset and gain registers to control the Red input channel. When register bit ACYC=1, `auto-cycling' is enabled, and the input channel switches to the next offset and gain registers in the sequence when a pulse is applied to the RSMP input pin. The sequence is Red Green Blue Red... offset and gain registers applied to the single input channel. A write to the Auto-cycle reset register (address 05h) will reset the sequence to a known state (Red registers selected). When auto-cycling is enabled, the RSMP pin cannot be used to control reset level clamping. The CLMPCTRL bit may be used instead (enabled when high, disabled when low). NB, when auto-cycling is enabled, the RSMP pin cannot be used for reset sampling (i.e. CDS must be set to 0).
CONTROL INTERFACE
The internal control registers are programmable via the serial digital control interface. The register contents can be read back via the serial interface on pin OP[7]/SDO. Note: It is recommended that a software reset is carried out after the power-up sequence, before writing to any other register. This ensures that all registers are set to their default values (as shown in Table 7).
SERIAL INTERFACE: REGISTER WRITE
Figure 18 shows register writing in serial mode. Three pins, SCK, SDI and SEN are used. A six-bit address (a5, 0, a3, a2, a1, a0) is clocked in through SDI, MSB first, followed by an eight-bit data word (b7, b6, b5, b4, b3, b2, b1, b0), also MSB first. Each bit is latched on the rising edge of SCK. When the data has been shifted into the device, a pulse is applied to SEN to transfer the data to the appropriate internal register. Note all valid registers have address bit a4 equal to 0 in write mode.
SCK
SDI
a5
0
a3
a2
a1
a0
b7
b6
b5
b4
b3
b2
b1
b0
Address SEN
Data Word
Figure 18 Serial Interface Register Write A software reset is carried out by writing to Address "000100" with any value of data, (i.e. Data Word = XXXXXXXX).
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WM8214
SERIAL INTERFACE: REGISTER READ-BACK
Figure 19 shows register read-back in serial mode. Read-back is initiated by writing to the serial bus as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. Writing address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of corresponding register (a5, 0, a3, a2, a1, a0) to be output MSB first on pin SDO (on the falling edge of SCK). Note that pin SDO is shared with an output pin, OP[7], therefore OEB should always be held low and the OPD register bit should be set low when register read-back data is expected on this pin. The next word may be read in to SDI while the previous word is still being output on SDO.
SCK
SDI
a5
1 a3 a2 a1 a0
x
x
x
x
x
x
x
x
Address SEN SDO/ OP[7] OEB
Data Word
d7 d6 d5 d4 d3 d2 d1 d0
Output Data Word
Figure 19 Serial Interface Register Read-back
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NORMAL OPERATING MODES
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Table 4 below shows the normal operating modes of the device. The MCLK speed can be specified along with the MCLK:VSMP ratio to achieve the desired sample rate.
NUMBER OF CHANNELS 3
DESCRIPTION
CDS AVAILABLE YES
MAXIMUM SAMPLE RATE 13.33 MSPS
TIMING REQUIREMENTS MCLK max = 40Mhz Minimum MCLK:VSMP ratio = 3:1 MCLK max = 40Mhz Minimum MCLK:VSMP ratio = 2:1 MCLK max = 40Mhz Minimum MCLK:VSMP ratio = 1:1
CHANNEL MODE SETTINGS MONO = 0 TWOCHAN = 0 MONO = 0 TWOCHAN = 1 MONO = 1 TWOCHAN = 0
Three channel Pixel-by-Pixel Two channel Pixel-by-Pixel One channel Pixel-by-Pixel
2
YES
20 MSPS
1
YES
40 MSPS
Table 4 WM8214 Normal Operating Modes
Table 5 below shows the different channel mode register settings required to operate the 8214 in 1, 2 and 3 channel modes.
MONO 0 0 1 1 1 1 1
TWOCHAN 0 1 0 0 0 0 1
CHAN[1:0] XX XX 00 01 10 11 XX
MODE DESCRIPTION 3-channel (colour mode) 2-channel (Blue PGA disabled) 1-channel (monochrome) mode. Red channel selected, Green and Blue PGAs disabled. 1-channel (monochrome) mode. Green channel selected, Red and Blue PGAs disabled. 1-channel (monochrome) mode. Blue channel selected, Red and Green PGAs disabled. Invalid mode Invalid mode
Table 5 Sampling Mode Summary
Note: Unused input pins should be connected to AGND.
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WM8214
The WM8214 has been designed to have a high degree of compatibility with previous generations of Wolfson AFEs. By setting the LEGACY register bit the input timing is made compatible with the WM819x and WM815x series of devices. Additional features such as the VSMP detect mode are also retained in LEGACY mode.
LEGACY MODE INFORMATION
LEGACY: PROGRAMMABLE VSMP DETECT CIRCUIT
The VSMP input is used to determine the sampling point and frequency of the WM8214. Under normal operation a pulse of 1 MCLK period should be applied to VSMP at the desired sampling frequency (as shown in the LEGACY Mode Timing Diagrams) and the input sample will be taken on the first rising MCLK edge after VSMP has gone low. However, in certain applications such a signal may not be readily available. The programmable VSMP detect circuit in the WM8214 allows the sampling point to be derived from any signal of the correct frequency, such as a CCD shift register clock, when applied to the VSMP pin. When enabled, by setting the VSMPDET control bit, the circuit detects either a rising or falling edge (determined by POSNNEG control bit) on the VSMP input pin and generates an internal VSMP pulse, INTVSMP. When POSNNEG = 1, a positive edge transition is detected and when POSNNEG = 0, a falling edge transition is detected. INTVSMP can optionally be delayed by a number of MCLK periods, specified by the VDEL[2:0] bits. Figure 20 shows the internal VSMP pulses that can be generated by this circuit for a typical clock input signal. The internal VSMP pulse is then applied to the timing control block in place of the normal VSMP pulse provided from the input pin. The sampling point occurs on the first rising MCLK edge after this internal VSMP pulse, as shown in the LEGACY Mode Timing Diagrams.
MCLK INPUT PINS VSMP
POSNNEG = 1 (VDEL = 000) INTVSMP (VDEL = 001) INTVSMP (VDEL = 010) INTVSMP (VDEL = 011) INTVSMP (VDEL = 100) INTVSMP (VDEL = 101) INTVSMP (VDEL = 110) INTVSMP (VDEL = 111) INTVSMP POSNNEG = 0 (VDEL = 000) INTVSMP (VDEL = 001) INTVSMP (VDEL = 010) INTVSMP (VDEL = 011) INTVSMP (VDEL = 100) INTVSMP (VDEL = 101) INTVSMP (VDEL = 110) INTVSMP (VDEL = 111) INTVSMP
VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS
Figure 20 Internal VSMP Pulses Generated by Programmable VSMP Detect Circuit
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LEGACY OPERATING MODES
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Table 6 summarises the most commonly used modes, the clock waveforms required and the register contents required for CDS and non-CDS operation. MODE DESCRIPTION CDS AVAILABLE MAX SAMPLE RATE 6.67MSPS SENSOR INTERFACE DESCRIPTION The 3 input channels are sampled in parallel. The signal is then gain and offset adjusted before being multiplexed into a single data stream and converted by the ADC, giving an output data rate of 20MSPS max. As mode 1 except: Only one input channel at a time is continuously sampled. TIMING REQUIREMENTS MCLK max = 40MHz MCLK: VSMP ratio is 2n:1 , n 3 REGISTER CONTENTS WITH CDS SetReg1: 83(hex) REGISTER CONTENTS WITHOUT CDS SetReg1: 81(hex)
1
Colour Pixel-by-Pixel
Yes
2
Monochrome/ Colour Line-by-Line
Yes
6.67MSPS
MCLK max = 40MHz MCLK: VSMP ratio is 2n:1 , n 3 MCLK max = 40MHz MCLK: VSMP ratio is 3:1 MCLK max = 40MHz MCLK: VSMP ratio is 2:1
SetReg1: 87(hex)
SetReg1: 85(hex)
3
Fast Monochrome/ Colour Line-by-Line
Yes
13.33MSPS Identical to mode 2
Identical to mode 2 plus SetReg3: bits 5:4 must be set to 0(hex) CDS not possible
Identical to mode 2
4
Maximum speed Monochrome/ Colour Line-by-Line
No
20MSPS
Identical to mode 2
SetReg1: C5(hex)
Table 6 WM8214 Legacy Operating Modes Notes: 1. 2. In Monochrome mode, SetReg3 bits 7:6 determine which input is to be sampled. For Colour Line-by-Line, set control bit LINEBYLINE. For input selection, refer to Table 4, Colour Selection Description in Line-by-Line Mode.
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WM8214
The following diagrams show 8-bit multiplexed output data and MCLK, VSMP and input video requirements for operation of the most commonly used modes as shown in Table 6. The diagrams are identical for both CDS and non-CDS operation. Outputs from RINP, GINP and BINP are shown as R, G and B respectively. X denotes invalid data.
LEGACY MODE TIMING DIAGRAMS
Figure 21 Mode 1 Operation
Figure 22 Mode 2 Operation
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Figure 23 Mode 3 Operation
Figure 24 Mode 4 Operation
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WM8214
DEVICE CONFIGURATION
REGISTER MAP
The following table describes the location of each control bit used to determine the operation of the WM8214.
ADDRESS
DESCRIPTION
DE F (he x)
RW b7 b6 b5 b4
BIT b3 b2 b1 b0
000001 (01h) Setup Reg 1 000010 (02h) Setup Reg 2 000011 (03h) Setup Reg 3 000100 (04h) Software Reset 000101 (05h) Auto-cycle Reset 000110 (06h) Setup Reg 4 000111 (07h) Setup Reg 5 001000 (08h) Setup Reg 6 001001 (09h) Reserved 001010 (0Ah) Reserved 001011 (0Bh) Reserved 001100 (0Ch) Reserved 100000 (20h) DAC Value (Red) 100001 (21h) DAC Value (Green) 100010 (22h) DAC Value (Blue) 100011 (23h) DAC Value (RGB) 100100 (24h) PGA Gain LSB (Red) 100101 (25h) PGA Gain LSB (Green) 100110 (26h) PGA Gain LSB (Blue) 100111 (27h) PGA Gain LSB (RGB) 101000 (28h) PGA Gain MSBs (Red) 101001 (29h) PGA Gain MSBs (Green) 101010 (2Ah) PGA Gain MSBs (Blue) 101011 (2Bh) PGA Gain MSBs (RGB)
03 20 1F 00 00 00 00 20 00 00 00 00 80 80 80 00 00 00 00 00 0C 0C 0C 00
RW RW RW W W RW RW RW RW RW RW RW RW RW RW W RW RW RW W RW RW RW W
LEGACY DEL[1] CHAN[1]
MODE4LEG DEL[0] CHAN[0]
PGAFS[1] RLCDACRNG CDSREF [1]
PGAFS[0] LOWREFS CDSREF [0]
TWOCHAN OPD RLCDAC[3]
MONO INVOP RLCDAC[2]
CDS OPFORM[1] RLCDAC[1]
EN OPFORM[0] RLCDAC[0]
0 0 0 0 0 0 0 DACR[7] DACG[7] DACB[7] DACRGB[7] 0 0 0 0 PGAR[8] PGAG[8] PGAB[8] PGARGB[8]
0 VRXPD CLAMPCTRL 0 0 0 0 DACR[6] DACG[6] DACB[6] DACRGB[6] 0 0 0 0 PGAR[7] PGAG[7] PGAB[7] PGARGB[7]
0 ADCREFPD RLCEN 0 0 0 0 DACR[5] DACG[5] DACB[5] DACRGB[5] 0 0 0 0 PGAR[6] PGAG[6] PGAB[6] PGARGB[6]
0 VRLCDACPD POSNNEG 0 0 0 0 DACR[4] DACG[4] DACB[4] DACRGB[4] 0 0 0 0 PGAR[5] PGAG[5] PGAB[5] PGARGB[5]
INTM[1] ADCPD VDEL[2] 0 0 0 0 DACR[3] DACG[3] DACB[3] DACRGB[3] 0 0 0 0 PGAR[4] PGAG[4] PGAB[4] PGARGB[4]
INTM[0] BLUPD VDEL[1] 0 0 0 0 DACR[2] DACG[2] DACB[2] DACRGB[2] 0 0 0 0 PGAR[3] PGAG[3] PGAB[3] PGARGB[3]
ACYC GRNPD VDEL[0] 0 0 0 0 DACR[1] DACG[1] DACB[1] DACRGB[1] 0 0 0 0 PGAR[2] PGAG[2] PGAB[2] PGARGB[2]
LINEBYLINE REDPD VSMPDET 0 0 0 0 DACR[0] DACG[0] DACB[0] DACRGB[0] PGAR[0] PGAG[0] PGAB[0] PGARGB[0] PGAR[1] PGAG[1] PGAB[1] PGARGB[1]
Table 7 Register Map
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REGISTER MAP DESCRIPTION
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The following table describes the function of each of the control bits shown in Table 7.
REGISTER Setup Register 1
BIT NO 0
BIT NAME(S) EN
DEFAULT 1
DESCRIPTION Global Enable 0 = complete power down, 1 = fully active (individual blocks can be disabled using individual power down bits - see setup register 5). Select correlated double sampling mode: 0 = single ended mode, 1 = CDS mode. Sampling mode select (see Table 5 for further details): 0 = other mode (2 or 3-channel) 1 = Monochrome (1-channel) mode. Input channel selected by CHAN[1:0] register bits, unused channels are powered down. Sampling mode select (see Table 5 for further details): 0 = other mode (1 or 3-channel) 1 = 2-channel mode. Inputs channels are Red and Green, Blue channel is powered down. Offsets PGA output to optimise the ADC range for different polarity sensor output signals. Zero differential PGA input signal gives: 0x = Zero output from the PGA (Output code=32767) 10 = Full-scale positive output (OP=65535) - use for negative going video. NB, Set INVOP=1 if zero differential input should give a zero output code with negative going video. 11 = Full-scale negative output (OP=0) - use for positive going video This bit has no effect when LEGACY=0. Set this bit when operating in LEGACY MODE4: 0 = other modes, 1 = LEGACY MODE4. Makes the WM8214 timing compatible with the WM819x and WM815x AFE families. 0 = Normal timing 1 = Enable LEGACY timing. Requires double rate MCLK and pixel rate VSMP input. RSMP pin performs same function as RLC/ACYC pin on WM819x devices.
1
CDS
1
2
MONO
0
3
TWOCHAN
0
5:4
PGAFS[1:0]
00
6
MODE4LEG
0
7
LEGACY
0
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Production Data REGISTER Setup Register 2 BIT NO 1:0 BIT NAME(S) OPFORM[1:0] DEFAULT 0 DESCRIPTION
WM8214
Determines the output data format. x0 = 8-bit multiplexed (8+8 bits) 01 = 8-bit parallel (8-MSBs only) 11 = 4-bit multiplexed mode (4+4+4+4 bits). This mode is only valid when LEGACY=1. Digitally inverts the polarity of output data. 0 = negative going video gives negative going output, 1 = negative-going video gives positive going output data. Output Disable. This works with the OEB pin to control the output pins. 0=Digital outputs enabled, 1=Digital outputs high impedance OEB (pin) 0 0 1 1 OPD 0 1 0 1 OP pins Enabled High Impedance High Impedance High impedance
2
INVOP
0
3
OPD
0
4
LOWREFS
0
Reduces the ADC reference range (2*[VRT-VRB]), thus changing the max/min input voltages. 0= ADC reference range = 2.0V 1= ADC reference range = 1.2V
5
RLCDACRNG
1
Sets the output range of the RLCDAC. 0 = RLCDAC ranges from 0 to AVDD (approximately), 1 = RLCDAC ranges from 0 to VRT (approximately). Controls the latency from sample to data appearing on output pins Latency DEL 00 01 10 11 LEGACY=0 All timing modes 7 MCLK periods 8 MCLK periods 9 MCLK periods 10 MCLK periods LEGACY=1 timing modes 1-2,4-6 16.5 MCLK periods 18.5 MCLK periods 20.5 MCLK periods 22.5 MCLK periods LEGACY=1 timing mode 3 23.5 MCLK periods 26.5 MCLK periods 29.5 MCLK periods 31.5 MCLK periods
7:6
DEL[1:0]
00
Setup Register 3
3:0
RLCDAC[3:0]
1111
Controls RLCDAC driving VRLC/VBIAS pin to define single ended signal reference voltage or Reset Level Clamp voltage. See Electrical Characteristics section for ranges. When LEGACY=0 these register bits have no effect. CDS mode reset timing adjust. 00 = Advance reset sample by 1 MCLK period (relative to default). 01 = Default reset sample position. 10 = Delay reset sample by 1 MCLK period (relative to default) 11 = Delay reset sample by 2 MCLK periods (relative to default) When MONO=0 these register bits have no effect Monochrome mode channel select. 00 = Red channel select 10 = Blue channel select 01 = Green channel select 11 = Reserved Any write to Software Reset causes all cells to be reset. It is recommended that a software reset be performed after a power-up before any other register writes. Any write to Auto-cycle Reset causes the auto-cycle counter to reset to RINP. This function is only required when LINEBYLINE = 1.
5:4
CDSREF[1:0]
01
7:6
CHAN[1:0]
00
Software Reset Auto-cycle Reset
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REGISTER Setup Register 4 BIT NO 0 BIT NAME(S) LINEBYLINE DEFAULT 0 DESCRIPTION
Production Data
Selects line by line operation. Line by line operation is intended for use with systems which operate one line at a time but with up to three colours shared on that one output. 0 = normal operation, 1 = line by line operation. When line by line operation is selected MONO is forced to 1 and CHAN[1:0] to 00 internally, ensuring that the correct internal timing signals are produced. Green and Blue PGAs are also disabled to save power. When LINEBYLINE = 0 this bit has no effect. When LINEBYLINE = 1 this bit determines the function of the RSMP input pin and the offset/gain register controls. 0 = RSMP pin enabled for either reset sampling (CDS) or Reset Level Clamp control. Internal selection of gain/offset multiplexers using INTM[1:0] register bits. 1 = Auto-cycling enabled by pulsing the RSMP input pin. This means that each time a pulse is applied to this pin the single input channel will switch to the next offset register and gain register in the sequence. The sequence is Red->Green->Blue->Red... offset and gain registers applied to the red input channel. When auto-cycling is enabled, the RSMP pin cannot be used to control reset level clamping. The CLMPCTRL bit may be used instead (enabled when high, disabled when low). NB, when auto-cycling is enabled, the RSMP pin cannot be used for reset sampling (i.e. CDS must be set to 0). When LINEBYLINE=0 or ACYC=1 this bit has no effect. When LINEBYLINE=1 and ACYC=0: Controls the PGA/offset mux selector: 00 = Red PGA/Offset registers applied to input channel 01 = Green PGA/Offset registers applied to input channel 10 = Blue PGA/Offset registers applied to input channel 11 = Reserved.
1
ACYC
0
3:2
INTM[1:0]
00
7:4 Setup Register 5 0 1 2 3
Reserved REDPD GRNPD BLUPD ADCPD
0000 0 0 0 0
Must be set to 0 When set powers down red S/H, PGA When set powers down green S/H, PGA When set powers down blue S/H, PGA When set powers down ADC. Allows reduced power consumption without powering down the references which have a long time constant when switching on/off due to the external decoupling capacitors. When set powers down 4-bit RLCDAC, setting the output to a high impedance state and allowing an external reference to be driven in on the VRLC/VBIAS pin. When set disables VRT, VRB buffers to allow external references to be used. When set disables VRX buffer to allow an external reference to be used. Must be set to 0 When LEGACY=0 this register bit has no effect. When LEGACY=1: 0 = Normal operation, signal on VSMP input pin is applied directly to Timing Control block. 1 = Programmable VSMP detect circuit is enabled. An internal synchronisation pulse is generated from signal applied to VSMP input pin and is applied to Timing Control block in place of VSMP. When LEGACY=0 or VSMPDET=0 these bits have no effect. The VDEL bits set a programmable delay from the detected edge of the signal applied to the VSMP pin. The internally generated pulse is delayed by VDEL MCLK periods from the detected edge. See Figure 20, Internal VSMP Pulses Generated for details.
4
VRLCDACPD
0
5 6 7 Setup Register 6 0
ADCREFPD VRXPD Reserved VSMPDET
0 0 0 0
3:1
VDEL[2:0]
000
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Production Data REGISTER BIT NO 4 BIT NAME(S) POSNNEG DEFAULT 0 DESCRIPTION
WM8214
When LEGACY=0 or VSMPDET=0 this bit has no effect. When LEGACY=1 and VSMPDET=1 this bit controls whether positive or negative edges on the VSMP input pin are detected: 0 = Negative edge on VSMP pin is detected and used to generate internal timing pulse. 1 = Positive edge on VSMP pin is detected and used to generate internal timing pulse. See Figure 20 for further details. Reset Level Clamp Enable. When set Reset Level Clamping is enabled. The method of clamping is determined by CLAMPCTRL and LEGACY. In LEGACY mode clamping will still occur on every pixel at a time defined by the CDSREF[1:0] bits. This bit has no effect if LEGACY=1. See Table 2 for more information. 0 = RLC switch is controlled directly from RSMP input pin: RSMP = 0: switch is open RMSP = 1: switch is closed 1 = RLC switch is controlled by logical combination of RSMP and VSMP. RSMP && VSMP = 0: switch is open RSMP && VSMP = 1: switch is closed
5
RLCEN
1
6
CLAMPCTRL
0
7 Offset DAC (Red) Offset DAC (Green) Offset DAC (Blue) Offset DAC (RGB) PGA Gain LSB (Red) PGA Gain LSB (Green) PGA Gain LSB (Blue) PGA Gain LSB (RGB) PGA gain MSBs (Red) PGA gain MSBs (Green) PGA gain MSBs (Blue) PGA gain MSBs(RGB) 0 0 7:0 7:0 7:0 7:0 0
Reserved DACR[7:0] DACG[7:0] DACB[7:0] DACRGB[7:0] PGAR[0]
0 10000000 10000000 10000000 0 0
Must be set to 0 Red channel 8-bit offset DAC value (mV) = 260*(DACR[7:0]-127.5)/127.5 Green channel 8-bit offset DAC value (mV) = 260*(DACG[7:0]-127.5)/127.5 Blue channel 8-bit offset DAC value (mV) = 260*(DACB[7:0]-127.5)/127.5 A write to this register location causes the red, green and blue offset DAC registers to be overwritten by the new value This register bit forms the LSB of the red channel PGA gain code. PGA gain is determined by combining this register bit and the 8 MSBs contained in register address 28 hex. This register bit forms the LSB of the green channel PGA gain code. PGA gain is determined by combining this register bit and the 8 MSBs contained in register address 29 hex. This register bit forms the LSB of the blue channel PGA gain code. PGA gain is determined by combining this register bit and the 8 MSBs contained in register address 2A hex.
0
PGAG[0]
0
PGAB[0]
0
PGARGB[0]
0
Writing a value to this location causes red, green and blue PGA LSB gain values to be overwritten by the new value.
7:0
PGAR[8:1]
00001100
Bits 8 to 1 of red PGA gain. Combined with red LSB register bit to form complete PGA gain code. This determines the gain of the red channel PGA according to the equation: Red channel PGA gain (V/V) = 0.66 + PGAR[8:0]x7.34/511 Bits 8 to 1 of green PGA gain. Combined with green LSB register bit to form complete PGA gain code. This determines the gain of the green channel PGA according to the equation: Green channel PGA gain (V/V) = 0.66 + PGAG[8:0]x7.34/511 Bits 8 to 1 of blue PGA gain. Combined with blue LSB register bit to form complete PGA gain code. This determines the gain of the blue channel PGA according to the equation: Blue channel PGA gain (V/V) = 0.66 + PGAB[8:0]x7.34/511 A write to this register location causes the red, green and blue PGA MSB gain registers to be overwritten by the new value.
7:0
PGAG[8:1]
00001100
7:0
PGAB[8:1]
00001100
7:0
PGARGB[8:1]
0
Table 8 Register Control Bits
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WM8214 APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
DVDD1 DVDD2 3 10 C1 C2 AVDD 21 C3 DGND AGND 1 RINP GINP BINP VRT VRX VRB 24 25 23 C6 C7 C8 C4 C5 AVDD AGND1 AGND2 22 2 AGND DVDD1 DVDD2 DGND 8
Production Data
Video Inputs
28 27
26 C9
VRLC/VBIAS AGND
WM8214
AGND 7 MCLK VSMP RSMP OP[7]/SDO OP[6] OP[5] OP[4] OP[3] 12 11 SCK SDI SEN OP[2] OP[1] OP[0] 5 6 20 19 18 17 16 15 14 13 DVDD1 DVDD2 + C10 + C11 AVDD + C12
Timing Signals
Output Data Bus
DGND
AGND
Interface Controls
9
4
OEB
NOTES: 1. C1-9 should be fitted as close to WM8214 as possible. 2. AGND and DGND should be connected as close to WM8214 as possible.
Figure 25 External Components Diagram
RECOMMENDED EXTERNAL COMPONENT VALUES
COMPONENT REFERENCE C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 SUGGESTED VALUE 100nF 100nF 100nF 10nF 1F 100nF 100nF 100nF 100nF 10F 10F 10F DESCRIPTION De-coupling for DVDD1. De-coupling for DVDD2. De-coupling for AVDD. High frequency de-coupling between VRT and VRB. Low frequency de-coupling between VRT and VRB (non-polarised). De-coupling for VRB. De-coupling for VRX. De-coupling for VRT. De-coupling for VRLC. Reservoir capacitor for DVDD1. Reservoir capacitor for DVDD2. Reservoir capacitor for AVDD.
Table 9 External Components Descriptions
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PD, Rev 4.4, August 2008 34
Production Data
WM8214
PACKAGE DIMENSIONS
DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm) DM007.E
b
28
e
15
E1
E
1
D
14
GAUGE PLANE
c A A2 A1 -C0.10 C
SEATING PLANE
L
0.25
L1
Symbols A A1 A2 b c D e E E1 L L1 REF: MIN ----0.05 1.65 0.22 0.09 9.90 7.40 5.00 0.55 0
o
Dimensions (mm) NOM --------1.75 0.30 ----10.20 0.65 BSC 7.80 5.30 0.75 1.25 REF o 4 JEDEC.95, MO-150
MAX 2.0 0.25 1.85 0.38 0.25 10.50 8.20 5.60 0.95 8
o
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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WM8214 IMPORTANT NOTICE
Production Data
Wolfson Microelectronics plc ("Wolfson") products and services are sold subject to Wolfson's terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson's products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer's own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party's products or services does not constitute Wolfson's approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson's standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person's own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person.
ADDRESS:
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB
Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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